 |
Single issue, 7-stage pipeline
|
| |
| • |
Significant clock frequency
improvement over 5 and 6-stage pipeline designs |
|
 |
Optional MMU |
| |
| • |
Virtual-to-physical address
translation |
| • |
Support Linux OS |
|
 |
Optional Custom Engine |
| |
| • |
Support 32-bit sign/un-sign
multiply and divider |
|
 |
Support local instruction memory
and/or cache memory with configurable size |
 |
Support local data memory and/or
cache memory with configurable size |
 |
Optional customer-defined instruction
extensions |
 |
Optional customer-defined coprocessors
|
| |
| • |
Add up to 3 coprocessors
to support complex operations |
|
 |
Low-Overhead Interrupts |
| |
| • |
Sixty-three prioritized
interrupts, unique vector for each interrupt |
|
 |
Support non-maskable interrupt
and precise/imprecise bus error exception |
 |
AMBA 2.0 compliant (AHB 2.0
master) |
 |
32/16-bit hybrid instruction
mode and parallel conditional execution for high |
| |
code density |
 |
Optional SJTAG Debug |
| |
| • |
Implements of SJTAG 1.0.0
specification |
| • |
User-configurable SJTAG
breakpoints |
|
 |
Easy ASIC Integration |
| |
| • |
Single positive-edge clocking |
| • |
Fully synchronous design |
| • |
Supports for popular EDA
tools |
|