Sunplus - Products - Sunplus 32-bit CPU

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Sunplus 32-bit CPU S⁺core™

High Performance and Low Power Processor Core for SoC Applications

Development Tools now available!

The S⁺core™ is Taiwan's first self-defined 32-bit RISC CPU with Sunplus-owned instruction set architecture (ISA). The ISA has 32/16-bit hybrid instruction mode and parallel conditional execution for high code density, high performance and versatile application. The micro-architecture includes AMBA bus for SoC integration, coprocessor and custom engine interface for function flexibility, and SJTAG for efficient debugging and In-Circuit Emulation (ICE).

The user friendly development environment including S+core IDE, simulator, optimization GNU C/C++ compiler and GDB enable users to develop the high quality application in fast time.

Now it's applied to the Sunplus SPG290, High Performance SoC for Home and Personal Entertainment Platform, which will enter to mass production in the end of this year. Furthermore S⁺core™ will be applied to more and more high-performance applications like information, communication, car-electron and industrial.

FEATURES

Single issue, 7-stage pipeline

•	Significant clock frequency improvement over 5 and 6-stage pipeline designs

Optional MMU

•	Virtual-to-physical address translation
•	Support Linux OS

Optional Custom Engine

•	Support 32-bit sign/un-sign multiply and divider

Support local instruction memory and/or cache memory with configurable size

Support local data memory and/or cache memory with configurable size

Optional customer-defined instruction extensions

Optional customer-defined coprocessors

•	Add up to 3 coprocessors to support complex operations

Low-Overhead Interrupts

•	Sixty-three prioritized interrupts, unique vector for each interrupt

Support non-maskable interrupt and precise/imprecise bus error exception

AMBA 2.0 compliant (AHB 2.0 master)

32/16-bit hybrid instruction mode and parallel conditional execution for high

code density

Optional SJTAG Debug

•	Implements of SJTAG 1.0.0 specification
•	User-configurable SJTAG breakpoints

Easy ASIC Integration

•	Single positive-edge clocking
•	Fully synchronous design
•	Supports for popular EDA tools

ACHIVEMENTS

	The first self-defined instruction set architecture 32-bit RISC CPU in Taiwan.
	Established high-efficient development platform with integrated software/hardware tools.
	It's silicon-proved and performances have been verified successfully.
	Obtained over 40 patents worldwide with complete & entire IPs.
	Authorized CIC the educational version and to further joint-promote Taiwan IC industry with goverment and academia.
	It has been applied to Physical IC product.

AWARDS

	Awarded "The National Invention and Creation Award, Golden Medal" from Taiwan Ministry of Economic Affairs in Spetember 2007
	Awarded "Outstanding Contribution to the Industry Award" from Taiwan Ministry of Economic Affairs in September 2006.
	Awarded "The National Invention and Creation Award, Silver Medal" from Taiwan Ministry of Economic Affairs in Spetember 2006
	Awarded “The Best Originality Award” from Taiwan NSoC in May 2006

PRODUCT APPLICATIONS

SPG290 - SoC for Home and Personal Entertainment Platform

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